This invention relates to a delay time control circuit to be used in a semiconductor test system, and more particularly, to a delay time control circuit for controlling a signal propagation delay time of semiconductor gate circuits to generate test signals having accurate delay times for a semiconductor test system.
In testing a semiconductor device by a semiconductor test system, a semiconductor device under test is provided with various test signals with varying timings. The semiconductor test system must generate the test signals while accurately controlling timings of the test signals. Typically, such timing differences are produced by delay circuits formed of CMOS circuits.
Such a delay circuit formed of semiconductor circuits usually includes a series of CMOS gates, typically inverters, each of which has a certain propagation delay time. A delay time is determined by selecting the number of inverters serially connected in the delay circuit. However, the transmission delay times in the CMOS circuits are subject to surrounding temperature changes and/or voltage changes, which decrease the accuracy of the delay times in the semiconductor test system. Therefore, to maintain the high accuracy or to stabilize the delay times in the semiconductor test system, the following methods or technologies are used in the conventional delay circuits having the semiconductor gates, typically CMOS gates, as delay elements.
In one conventional method, a heater is provided in an LSI (large scale integrated) circuit having CMOS gate delay circuits. The heater is positioned close to the CMOS gate delay circuits in the LSI. A delay time detector is also provided in the LSI circuit or in the close proximity of the LSI circuit to detect the delay time changes in the CMOS gate delay circuits. Since the delay times in the CMOS gates vary with the changes of the surrounding temperature, the heater is controlled so as to maintain the delay times of the CMOS gates constant based on the delay time changes detected by the delay time detector.
However, in this conventional method, an overall power consumption in the LSI circuit increases since the additional power is consumed to raise the internal temperature of the LSI circuit. Namely, to maintain the constant delay time, electric currents must be provided to the heater so as to control the internal temperature and thus the delay times in the CMOS delay circuit. Thus, it is not possible to decrease the power consumption in the LSI circuit. Further, additional circuit components are inevitable such as semiconductor cells to be used as the heater and the delay time detector.
In the other conventional method, an overall number of pulses or total frequencies in the delay circuit is controlled to be a constant value. Since the heat generation by the CMOS gates is proportional to the number of pulses or the overall frequency provided to the CMOS gates, i.e., the number of changes in the state (high or low) in the CMOS gates, it has been attempted to maintain the temperature of the CMOS gate delay circuit constant by controlling the overall number of pulses in the delay circuit constant.
For so doing, a dummy circuit formed of CMOS gates is provided in the LSI circuit to receive a certain number of pulses to supplement the pulses which is short in the actual CMOS delay circuit to make the overall number of pulses to be equal to the predetermined value. For example, in case where the predetermined overall number of pulses in one second is 20,000,000 and the actual number of pulses provided to the CMOS gate delay circuit is 2,000,000 to form a specific test signal, 8,000,000 pulses are generated to be provided to the dummy CMOS circuit.
However, in this conventional method, as in the first example, the overall power consumption in the LSI circuit increases since the additional power is consumed in the dummy CMOS circuit by the action of the supplemental number of pulses to make the overall number of pulses in the LSI circuit constant. Namely, to maintain the constant delay time, additional pulses must be provided to the dummy circuit so as to maintain the overall number of pulses constant. This is because to control the overall number of pulses to maintain the constant value is to control the internal temperature constant and also the delay times in the CMOS delay circuit constant.
Thus, in this example, it is not possible to decrease the power consumption in the LSI circuit since the additional power consumption is always necessary to stabilize the delay times. Further, in addition to the dummy CMOS circuit as mentioned above, further additional circuit components are necessary such as a circuit for detecting the number of pulses provided to the CMOS delay circuit and a circuit which generates the supplemental number of pulses for the dummy circuit.
In the further conventional method, source voltages to the CMOS gates delay circuit are controlled to stabilize the delay time of the delay circuit. As noted above, the delay times in the CMOS gates vary depending on the source voltages supplied to the CMOS gates. Thus, in this method, the delay times in the CMOS gates are monitored and a control voltage is feedbacked to adjust the source voltages to the CMOS gates to control the delay times constant.
In this method, however, as in the above two examples, the power consumption in the semiconductor test system increases. This is because the process of controlling the voltage sources must involve voltage drops in source voltage generating circuits connected to the CMOS gates. Thus the source voltage level for this method must be larger than an ordinary source voltage level to secure a certain control voltage range.
Furthermore, in this method of controlling the source voltages to the CMOS gates, since the change in the delay time in response to the change of the source voltage is small, an additional control means is usually necessary to compensate the delay time variance between each CMOS gates. For example, to maintain the delay time of the CMOS gates constant, output capacitance of some of the CMOS gates must also be controlled in addition to the control of the source voltages. Therefore, the number of circuit components or an overall circuit size increases in this example.
Moreover, in all of the above three conventional examples, although the delay times can be controlled to be a constant value, it is not possible to control a very small amount of delay time for each CMOS gate.
It is, therefore, an object of the present invention to provide a delay time control circuit for a semiconductor test system which is capable of controlling the delay time of a semiconductor gate delay circuit with high accuracy and stability without involving a large increase of power consumption in the overall delay circuit.
It is another object of the present invention to provide a delay time control circuit for a semiconductor test system which is capable of controlling the delay time of a semiconductor gate delay circuit with high accuracy and stability with a minor increase in circuit components.
It is a further object of the present invention to provide a delay time control circuit for a semiconductor test system which is capable of controlling the delay time of a semiconductor gate delay circuit with high accuracy and stability by controlling positive and negative gate control voltages of each semiconductor gate so that the delay time can be adjusted with high resolution.
In order to achieve the above objective, in the delay time control circuit of the present invention, the delay time change is monitored as a change of a duty ratio which is converted to a DC voltage. The DC voltage is compared with a reference voltage, and the difference between the two voltages is used to control a gate voltage for each CMOS gate.
Namely, the delay time control circuit of the present invention, for controlling delay times of a logic circuit which determines timings of test signals in a semiconductor test system, includes: a delay circuit having a plurality of serially connected semiconductor gates which are the same type of semiconductor gates as in the logic circuit; a pulse signal supplied to the delay circuit; a first group of gates which is a set of semiconductor gates in an input side of the semiconductor gates wherein the first group of gates generates a reset pulse based on the pulse signal; a second group of gates which is a set of semiconductor gates in an output side of the semiconductor gates wherein the second group of gates generates a set pulse based on the pulse signal; a delay-duty converter which is set by the set pulse from the second group of gates and is reset by the reset pulse by the first group of gates; an integrator which integrates an output signal of the delay-duty converter to produce an average voltage indicating a duty cycle of the output signal of the flip-flop; a first delay time control voltage generator which compares the average voltage from the integrator and a reference voltage indicating a delay time for the logic circuit and generates a first control voltage which is applied to the logic circuit and the delay circuit; and a second delay time control voltage generator which receives the first control voltage from the first delay time control voltage generator and generates a second control voltage which is symmetrical to the first control voltage and is applied to the logic circuit and the delay circuit.
In another aspect of the present invention, a delay time control circuit for controlling delay times of a logic circuit which determines timings of test signals in a semiconductor test system is comprised of: a delay circuit having a plurality of series connected semiconductor gates; a pulse generator for providing a pulse signal to the delay circuit; a delay-duty converter which is driven by an input pulse signal of the delay circuit and an output pulse signal of the delay circuit; an integrator which integrates an output signal of the delay-duty converter to produce an average voltage indicating a duty cycle of the output signal of the delay-duty converter; and a delay time control voltage generator which compares the average voltage from the integrator and a reference voltage indicating a delay time for the logic circuit and generates a control voltage which is applied to the logic circuit and the delay circuit.
In the further aspect of the present invention, a delay time control circuit for controlling delay times of a logic circuit which determines timings of test signals in a semiconductor test system is comprised of: a delay circuit having a plurality of series connected semiconductor gates which forms a ring oscillator by connecting an output of the last semiconductor gate of the delay circuit to an input of a first semiconductor gate to form a closed loop; a pulse generator for generating a fixed pulse width signal every time when receiving an oscillation signal from the ring oscillator; an integrator which integrates an output signal of the pulse generator to produce an average voltage indicating a duty cycle of an output of the pulse generator; and a delay time control voltage generator which compares the average voltage from the integrator and a reference voltage indicating a delay time for the logic circuit and generates a control voltage which is applied to the logic circuit and the delay circuit.
According to the present invention, the delay time control circuit for the semiconductor test system can control the delay time of the semiconductor gate delay circuit with high accuracy and stability without involving a large increase of power consumption in the delay circuit.
Further, in the present invention, the delay time control circuit can control the delay time of the semiconductor gate delay circuit with high accuracy and stability with only a minor increase in the circuit components. Furthermore, the delay time control circuit of the present invention can control the delay time of the semiconductor gate delay circuit with high resolution by controlling positive and negative gate control voltages of each semiconductor gate.